Digital Logic
Q71.
The following circuit implements a two-input AND gate using two 2-1 multiplexers. What are the values of X_1, X_2, X_3?Q72.
The control signal functions of a 4-bit binary counter are given below (where X is "don't care"): Assume that the counter and gate delays are negligible. If the counter starts at 0, then it cycles through the following sequence:Q74.
In a look-ahead carry generator, the carry generate function i G and the carry propagate function P_{i} for inputs A_{i} and B_{i} are given by: P_{i}=A_{i}\bigoplus B_{i} \; and \; G_{i}=A_{i}B_{i} The expressions for the sum bit S_{i} and the carry bit C_{i+1} of the look-ahead carry Combinational Circuit are given by: S_{i}=P_{i}\bigoplus C_{i} \; and \; C_{i+1}=G_{i}+P_{i}C_{i} Consider a two-level logic implementation of the look-ahead carry generator. Assume that all P_{i} and G_{i} are available for the carry generator circuit and that the AND and OR gates can have any number of inputs. The number of AND gates and OR gates needed to implement the look-ahead carry generator for a 4-bit Combinational Circuit with and S_{3},S_{2},S_{1},S_{0} as C_{4} its outputs are respectively:Q75.
How many 3-to-8 line decoders with an enable input are needed to construct a 6- to-64 line decoder without using any other logic gates?Q76.
The boolean function for a combinational circuit with four inputs is represented by the following Karnaugh map.Which of the product terms given below is an essential prime implicant of the function?Q77.
The circuit shown below implements a 2-input NOR gate using two 2-4 MUX (control signal 1 selects the upper input). What are the values of signals x, y and z?Q78.
We consider addition of two 2's complement numbers b_{n-1}b_{n-2}...b_{0} and a_{n-1}a_{n-2}...a_{0}. A binary Combinational Circuit for adding unsigned binary numbers is used to add the two numbers. The sum is denoted by c_{n-1}c_{n-2}...c_{0} and the carryout by c_{out} . Which one of the following options correctly identifies the overflow condition?Q79.
A circuit outputs a digit in the form of 4 bits. 0 is represented by 0000, 1 by 0001,..., 9 by 1001. A combinational circuit is to be designed which takes these 4 bits as input and outputs 1 if the digit \geq5, and 0 otherwise. If only AND, OR and NOT gates may be used, what is the minimum number of gates required?Q80.
A 4-bit carry look ahead Combinational Circuit, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the Combinational Circuit? Assume that the carry network has been implemented using two-level AND-OR logic.